Accurate Analytical Delay Models for VLSI Interconnects

Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. We develop an analytical delay model to incorporate inductance eeects into the delay estimate. Our method achieves delay estimates that are within 10% of SPICE-computed delay across a wide range of interconnect parameter values. We also give two example applications of our new analyses: (i) a condition under which interconnect delays can be minimized by introducing controlled ringing, and (ii) an extension of the New Delay model for estimation of delay in interconnect trees. 1 Overview Accurate calculation of propagation delay in VLSI interconnects is critical to the design of high speed systems. With the evolution of VLSI technology, transmission line eeects now play an important role in determining interconnect delays and system performance. Various techniques have been proposed for the simulation of interconnects. These techniques are based on either simulation techniques or (closed-form) analytical formulas. Direct simulation tools such as SPICE give the most accurate insight into arbitrary interconnect structures, but are computationally expensive. Transient simulation of lossy interconnects based on convolution techniques is presented in RP91, LK92]. Faster techniques based on moment computations are proposed in RGP91, RBR92, SK93]. The above methods, being simulation-based, are all computationally too expensive to be